Pic.1 shows DARM spectrum in the 2 different cofiguration (B1p, B1_PD3, B1_DC).

We performed the following noise injection (at least 1 min of clean data each).

We left DARM HH noise on almost all the time to allow measuring the DCP in different configurations.

We did a scan of the SR angular position (see pic 2). From a preliminary analysis of the DCP it seems that it is always below 100 Hz, but we want to confirm the goodness of the fit.

Optical spring was ~ 30 Hz. Around the end of the lock we tried to add a SRCL SET to decrease it and check a possible effect on DCP (HF frequency injected at that time). Data to be analyzed.

The fringe on B1p_DC was almost always higher than 0.05. Around 18 UTC it started to rise up to 1.1 (correspondingly to a decrease of OS). It was possible to reduce it by acting on SR alignment.

Unlike the lock of yesterday the BS AA was behaving correctly all the time. We uncomment its automatic engagement at carm null.

Concurrently with the BS drift control, also the WI F7 vertical damper has been added to the Automation; it is engaged in the CARM_NULL_1F state and disengaged in DOWN.

Figure 1 shows the OMC scan in CARM null. The sidebands are much worse that what was seen 6 months ago. The reanalysis of Feb 18 data is shown on Figure 2, the scan was done less linearly at the time, so it is harder to scale time into MHz, one would need a quadratic fit to do it properly, but the linear fit should be good enough.

So the sideband TEM00 are about a factor 2 smaller than 6 months ago, the very large imbalance is still roughly the same. The order 2 56MHz powers are roughly the same, which means the beam mode match is worse now by a factor 2 than 6 months ago. The theoretical expectation is 110mW of TEM00 per 56Mhz sideband and 2mW of TEM00 per 6MHz sideband.

Figure 3 and 4 shows three configuration that should be comparable, CITF with SR RH at 9.8W and CHRoCC at 0.43V, CARM null with SR RH at 9.8W and CHRoCC at 0.41V (lower correction as hot POP creates same of the same effect), CARM null in February.

The 56MHz TEM00 power now in CARM null (data point 2), is a factor 2 lower than the other two cases. The mode match is a bit worse than in CITF, and much worse than 6 months ago. The LSB/USB TEM00 balancing degrades when going from CITF to CARM null, but is comparable to what it was at CARM null 6 months ago.

Figure 1 shows the impact of the SRCL SET adjustments on the optical spring, which are very clear. Eleonora told me that SRCL SET is approximately in nm. It has also a clear impact on LSC_DARM_HF_LINE_PHI, which is the phase that in principle can be converted into a double cavity pole frequency estimation.

Figure 2 shows the conversion of that phase into DCP frequency in Hz (based on an offline crude estimation). There is a clear positive impact with the pole moving from 150Hz to 250Hz. This should be confirmed by studying more closely the noise injection that were done at that time. Note that at that time DARM was in DC read-out, while the calibration of the DCP offline computation was done using RF data. And the the shift from this afternoon hints at the phase changing for different read-out, likely due to the different DAQ delays for different photodiodes and RF vs DC channels. So the calibration of this pole is likely wrong, but the conclusion that SR offset can change significantly the DCP and make it better should remain true.