The new parameters now monitored and available as channels on the DAQ are:
- INJ_LNFS_REF: Power level of external reference signal. Valid range +10 to +16 dBm.
- INJ_LNFS_LOCK: Voltage of the lock detector. Valid range is 0.2 to 0.35 V.
- INJ_LNFS_PLL: Tuning port voltage on the oscillator. Valid range is +/-5 V
If the PLL is disabled then those values are not generated anymore by the LNFS. The choice has bee that, in this case, those channels take the fake value 20 in order to be well detected as out of range. (See Fig. 1).
A new flag LNFS has been added to the DMS which detect when one of those channels is out of range or the status of the Lnfs100 server (INJ_LNFS_INJLnfs100LNFS_State) is not ON (corresponding to 0, see https://logbook.virgo-gw.eu/virgo/?r=35618)
To be noted that the value of REF is marginal on the lower side of the valid range (See Fig. 2). This may be related to the spontaneous unlock (and corresponding change of phases) has been experienced in the past. It seems that the power level of external reference signal could be increased (since an attenuator is on the chain) and this will be possibly soon implemented.
This flags will help us to understand whether the "jumps" we see on the DAQ_LNFS_56/6MHz_phi are directly related with the PLL being on/off or not. What we have experienced these two last days is that everytime that there are such big jumps, we need to retune the demodulation phases, even though the modulation phase is supposed to compensate for these phase jumps (*phi_Corr*). Figure 1 shows the trend of the phases of B7 and B8 6MHz, B4 56MHz and the RFC 6MHz for the last two days.
As noticed by the commissioning crew, the phase-jumps were not due to the LNFS's PLL signal level (marginally on the low side), also because this configuration was used in the last years (and during the whole O2-run) without any problem.
Nevertheless today we went in the Injection Electronic Room (IER = "piscina") to measure the 10MHz signal sent from DAQ to the LNFS's PLL input as reference clock.
As visible (photo 1) the signal is a TTL 0-5V signal, not an AC-coupled LV-CMOS as thought.
Plugging it on a 50 Ohm load (AC-coupled scope) the amplitude is reduced a little bit (0-4V), not halved (photo 2), so the source impedance should be "near-zero" Ohm.
Measuring it on a 50 Ohm Spectrum Analyzer (via a DC-block capacitor) give a RF fundamental level of +18dBm (photo 3); considering the wasted power into harmonics, we can assume +20dBm (100mW/50Ohm) of power.
We then prepared a male-female BNC box with a series capacitor (0.1uF) as DC-block and a raw PI attenuator (100 Ohm, 56 Ohm, 100 Ohm); the level on the output is that way reduced to +9dBm on the fundamental, and plugging it on the LNFS PLL input we have over than 3dB (actually measured) of margin before an unlock (was previously 2dB).
The monitored PLL signal level is now increased from 9.9 to 11.6 (photo 4)
Extract from LNFS manual: "Ext Ref SMA input fo r the external 10 MHz reference. This input port has an impedance of 50 ohms. The external reference provided should be at10 MHz +/- 0.1 Hz with a level of +10 to +15 dBm."
We can see (photo 5) the spectrum and level of the signal as sent to the LNFS using the new adapter/box.
