At the end of the shift we performed a lock attempt up to LN2. We managed to reach DC readout but then the ITF shortly unlocked (see attached figure).
During this trial, the OMC did not manage to lock at first attempt, because the B1x_DC_DARM_norm_prod signal was not reaching the lock threshold set at 2000. We decreased this threshold to 1500 (done at 20h54 utc) and then the OMC locked successfully.
Low B1x_DC_DARM_norm_prod is a sign of poor OMC alignment (or that the DARM 491.3Hz is lower than during O4 at the same stage of the lock acquisition).
Figure 1. Looking at the previous lock where a few minutes where spent with B1 PD1/PD2 open, LSC_B1_DARM_OG looks anti-correlated with SDB1_LC_TX, with the gain higher when SDB1_LC_TX is lower. I have adjusted the B5 QD2 V offset from 350 to 300 this morning, as during the alignment yesterday the two looked equally good, but with an alignment signal which was a DC power fluctuating by a factor 10, so with very large error bars.
It would be useful to also enable the computation of the OMC dither error signals. In the automation these are computed only during the LN2 lock acquistion:
cm_send('SDB1_LC','AcRelayChTranSet','LC_B1_DARM_compute',1)
because each low noise actuator transition creates a large glitch in the computation of the error signal which takes several minutes to die down, as the signals are heavily low passed. Enabling the error signal computation for a few minutes once B1 PD1/PD2 are open without having any low noise transition after the computation starts could help finding if there is indeed an OMC misalignment or not.
Enabling the drift control loop at the same time as enabling the error signal computation, could also be a simple and efficient way of checking that, but with that loop closed the OMC alignment will be kicked if there is an actuator low noise transition cm_send('SDB1_LC','AcRelayChTranSet','LC_B1_DARM_enbl',1)
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