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AdV-INJ (Electro optical modulation system (EOM))
nocera - 21:34 Friday 18 November 2022 (57821) Print this report
RAMS Servo installation

R. Cavalieri, B. Montanari, F. Nocera, G. Sposito

today we installed the RAMS Servo.
As planned, we use this opportunity to rewire and cleanup most of the RF and DC Power Distribution cabling associated with INJ in the so called Piscina.
Since recent developments on the modulation front demanded the addition of a third EOM along the laser beam path (see entry 57819) and that it looks like this extra modulation Frequency (81.520 MHz, 81 for short) is going to need a RAMS Servo as well, we took this into consideration while rearranging units and cabling.

The addition of a 4th interferometer frequency (81 MHz) phase-locked to the other three (6, 8, and 56 MHz) requires to have a second synthesizer which can't be independent from the first one. We have adopted a Master-Slave configuration where one of the outputs of the second is used as a frequency reference for the first (10 MHz, +13 dBm). We have checked that this solution does not spoil Phase and Amplitude noise of the first, which specifications are stringent. No specification exists at this time for the 81 sideband.

This second synthesizer too can be driven remotely just as the first one, is connected on the same eth-RS232 bridge but on ch2.

The RAMS has been left on Manual (i.e., loop open) to allow the activity on the interferometer to restart as before the installation.

Measurements taken after the integration confirm the behavior of the beam modulation system is as expected. A thorough validation will require a locked interferometer and will likely come in the near future.

Some details about DAQ of RAMS Servo signals:

- Attenuation
    DAC sn 145 ch4 --> RAMS 6 MHz
    DAC sn 145 ch5 --> RAMS 8 MHz
    DAC sn 145 ch6 --> RAMS 56 MHz

- Out-of-the-Loop Sensor
    ADC sn 215 ch0 --> RAMS 6 MHz AC (it is the 6 MHz RAM)
    ADC sn 215 ch1 --> RAMS 6 MHz DC
    ADC sn 215 ch2 --> RAMS 8 MHz AC (it is the 8 MHz RAM)
    ADC sn 215 ch3 --> RAMS 8 MHz DC
    ADC sn 215 ch4 --> RAMS 56 MHz AC (it is the 56 MHz RAM)
    ADC sn 215 ch5 --> RAMS 56 MHz DC

for more details about RAMS electronics and performance see VIR-0627A-21.pdf

Comments to this report:
masserot - 0:33 Saturday 19 November 2022 (57825) Print this report
Images attached to this comment
masserot - 22:19 Monday 21 November 2022 (57839) Print this report

The gain of the  RAMS_OOTL_AC channels has been updated from 100 t0 1/100 at 2022-11-21-19h29m39-UTC

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