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AdV-COM (AdV commissioning (1st part) )
bersanetti, hoak - 7:36 Saturday 21 January 2017 (36132) Print this report
Locking shift - Back to 90% dark fringe, PRCL on B2_18MHz (3f)

Tonight's shift saw some progress, here is what we did:

  • first thing, we optimized the demodulation phase of the B2_8MHz signal (see Figure 1)
  • initially we had a few issues with the SSFS, as we noticed after an unlock that the SSFS_B4_Corr_DSP signal didn't go to 0 after the ITF unlocked; we found that the cause was most probably the fact that the Acl filter channels used to compute the RTPC correction were never reset, so the integrators could grow indefinitely and lead to big spikes at following attempts to close the SSFS loop; in order to heal this, we modified the SSFS_Ctrl process and added the SSFS_TRIG relay channel, which is triggered asimmetrically on the value of the main switch SSFS_ON; this relay is used to drive a reset condition to the filters, which then we saw behave correctly;
  • we locked the PRITF at half fringe again, and we gave a look at the B2_18MHz_I_PNORM signal, which is B2_18_MHz_I / (B1p_DC+B4_DC); this seemed good enough, even if noisier by nature, to hand-off PRCL to it; this was successfull, using a weight of -10 in the PRCL sensing matrix; afterwards, we modified the PRCL loop filter's rolloff, which is now done at 300Hz instead of 500Hz, due to the noisier signal (you can see in Figure 2 that now the loop is working much better); this worked well, so we decided to try and close the PRCL loop with this 3f signal from the start, and this has worked very nicely all night long. So now PRCL uses the B2_18MHz_I_PNORM signal (3f) by default; this has been already automated, although still in a "WIP" way: we are still using both the old PRCL gains and the new sensing weight, when things will be more fixed we will remove this duplication and rescale the gain; also, the Metatron state for this lock is the same used before, we hijacked it for the time being.
  • while the PR mirror is realigning, now we engage the boost filter for the MICH loop; this has helped a bit at low frequency, and the phase loss at higher frequency is not worrying;
  • as we moved towards dark fringe, we tested Michal's functions to close/reopen the B7 and B8 photodiode shutters; this has worked very nicely from the start, and now is default. In particular, the check whether the low power PDs (PD1) are open is done is the NARM_LOCK and WARM_LOCK nodes, while the automatic closing of the same photodiodes is done in the main sequence of the ITF_LOCK node, just after the switch between PD1 and PD2 in the B7B8_PD_SWITCH state;
  • at this point, we managed to get to darker fringe, eventually reaching again 90% dark fringe as it was done on monday (new MICH offset = 0.1) (se Figure 3); the lock did not last much in this condition, but we saw repeatedly that the whole lock acquisition up to MICH_SET = 0.3 is rather smooth now;

As of now, as we're still building it, the procedure we found working best is the the following:

  1. using Metatron, you can go up to the REDUCE_MICH_OFFSET state, which will bring the ITF to half fringe with PRCL on B2_3f, MICH on the new rescaled DC signal, CARM on SSFS and DARM still on normalized on B7-B8;
  2. at this point you can reduce the MICH offset to 0.3 by hand, while tweaking the gains:
    • cm_send('LSC_Acl','AcConstChSet','PRCL_GAIN',-600.0 ,20.0,'load')
      cm_send('LSC_Acl','AcConstChSet','DARM_GAIN',0.8 ,20.0,'load')
      cm_send('LSC_Acl','AcConstChSet','MICH_GAIN',175 ,20.0,'load')
      cm_send('LSC_Acl','AcConstChSet','MICH_SET',0.3 ,20.0,'apply')
  3. at this point the PD switch is needed, and this can be done with Metatron with the B7B8_PD_SWITCH;
  4. now you can reduce the MICH offset to 0.2, by hand again:
    • cm_send('LSC_Acl','AcConstChSet','PRCL_GAIN',-650.0 ,15.0,'load')
      cm_send('LSC_Acl','AcConstChSet','DARM_GAIN',1.0 ,15.0,'load')
      cm_send('LSC_Acl','AcConstChSet','MICH_SET',0.2 ,15.0,'apply')
  5. finally, you can reduce the MICH offset to 0.1:
    • cm_send('LSC_Acl','AcConstChSet','PRCL_GAIN',-700.0 ,15.0,'load')
      cm_send('LSC_Acl','AcConstChSet','DARM_GAIN',1.25 ,15.0,'load')
      cm_send('LSC_Acl','AcConstChSet','MICH_GAIN',200 ,15.0,'load')
      cm_send('LSC_Acl','AcConstChSet','MICH_SET',0.1 ,15.0,'apply')

The procedure will be automated as soon as possible, once the sequence is fine tuned and robust enough.

Three side notes:

  • we still see the MC mirror's Z position still move a lot over time: in Figure 4 you can see the trend during the last two locking shifts;
  • we still see quite a number of fast unlocks, probably due to the SSFS, as the IMC is the first thing to unlock; we didn't feel the need to adjust its gain as of now, as we didn't notice any particular instabilities; you can find an example at  3:10:29 UTC;
  • we didn't use the UGF monitors so far, as we were almost constantly not in a steady state, but the monitors are very useful for live tweaking of gains, and the servos will be definitely useful once we get to a steady state.
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Comments to this report:
genin, mantovani - 9:31 Saturday 21 January 2017 (36134) Print this report

Comment on the side note: we still see the MC mirror's Z position still move a lot over time: in Figure 4 you can see the trend during the last two locking shifts;

First of all, you should not wait the end of the shift before looking at the position of the MC end mirror.

The manual FmodErr Procedure is

open the Sc_IBCDMar1 DSP card  (or use whatever user interface you want)

1) Put the IMC AA in drift control mode (DRIFT_ENBL to 1)

2) Unlock the RFC (RFC_ENBL =0)

3) set the FmodErr line amplitude to 0.1 (open the ISYS_Acl from VPM)

4) tune slowly the Z position of the MC to bring the INJ_FmodErr_ACp to 0 (gname F0_Z_SET SaMCCD 4-5um/sec)

If you are not able to perform these steps put back the Sa_MC_F0_Z to the last position when FmodErr procedure has been done.

 

casanueva - 9:40 Saturday 21 January 2017 (36135) Print this report

Regarding the trigger on SSFS, I have looked to the code and I think that you have put a reset on the filter that calculates the digital noise introduced by the DSP not on the real one, which is not accesible. Obvisouly this needs to be confirmed by the experts from LAPP. However it does not go to 0 but it decreases down to a factor 10-30 or so, which the experts assured that it was normal and not the source of any problem.

masserot - 11:58 Saturday 21 January 2017 (36137) Print this report

I comfirms that the reset implemented in the SSFS_Ctrl  with the SSFS_TRIG relay performs only the reset on the filters calculating the digital noise running on the rtpc .

Today the only way to perform a reset of the filters running inside  the DSP it s to perform a "reload and reset"  of  the SSFS_Ctrl server or to stop and to restart it.

the DSP filter reset can be improved .

bersanetti - 16:02 Saturday 21 January 2017 (36141) Print this report

About the SSFS filter, I must have confused myself looking at the SSFS logic, but it did seem I had to reload & reset less often after the modification; probably then the issue is time related, and the reset hadn't been done in a while before the shift.

There should be some external procedure available to "users"; I can automate the reset of the SSFS_Ctrl process at each unlock, but it seems a bit overkill...

mwas - 10:48 Monday 23 January 2017 (36155) Print this report
Added the switch to B2_18MHz to the noise budget, and looked at the time with MICH_SET = 0.2
After adjusting the gains of the MICH/DARM loop gains by factors 2 to reproduce the right injections lines the models explains well the noise above 10Hz in MICH, DARM and PRCL.

DARM and MICH are dominated by the B7/B8 electronic noise
PRCL is dominated by B7/B8 electronic noise at 10-100Hz, and by B2 noise above 100Hz.

The optickle model used is on the svn ISC/optickle/models/PRITFnoise.m.
It also explains well the DC powers observed.

'PD' 'model' 'actual'
'B2' [ 7.2201] [ 7.5672]
'B4' [ 1.0896] [ 1.0982]
'B7' [ 1.1043] [ 1.0737]
'B8' [ 1.0728] [ 1.0358]
'B1p' [ 2.805] [ 2.885]
'B5' [0.99055] [ 0.78759]
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