Increasing the DARM offset did overcome some of the contamination and removed a second zero crossing. This allowed OMC1 locking (but only for very slow ramps).
OMC1 alignment should be checked to verify it is not the cause of the issue, otherwise the known slight astigmatism of the spare OMC installed last week is likely the reason.
A simple solution to be tested tomorrow is to use a double demodulation (first at 15kHz from the OMC length dither, then at 87.1Hz from the DARM line), which should remove the 56MHz order 1 mode from the OMC error signal. Hopefully the second OMC will filter out the leaking 56MHz order 1 mode from the DC readout signal.
Figure 1 shows the initial trials, in particular B1x_f1_DARM_i_DC2n shows a large dynamic linear evolution, and on B1x_f1_iDCn the second PDH signal overlapping with the main and causing almost a second zero crossing is visible.
Doing the lock acquisition with B1x_f1_DARM_i_DC2n and then handing off to the usual error signal worked, but was a bit limited by the low SNR of the signal.
Figure 2, and the end of shift remembered that the signal SNR can be easily increased by modulation the OMC1 PZT more. Changed the modulation from 0.01V to 0.1V. This makes the B1x_f1_DARM_i_DC2n signal much cleaner, but had some issue with the signal normalization.
The remaining steps should be re-adjusting the OMC1 length loop gain and checking the automation.
