The unlocks due to DARM oscillating at 27 Hz are caused by the fact that lately, even if OMC1 locks at the same B1s2 power ~ 1.5 mW, the intercalibration between RF and DC readout has changed and DARM falls down to the lower end of the stability region and sometimes unlocks at this stage. This has been cured for the time being by changing the DARM gain at the same time of the hand-off of the error signal; however, since the same change of the gain happens in the opposite way a bit earlier in the lock acquisition, it makes more sense to recalibrate the DC error signals, which should only make the final DARM gain to be changed and the DC readout lock acquisition smoother.